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Google

RTL Design Manager, CPU, Silicon

Taipei, Taiwan

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
  • 4 years of experience in people management, developing employees.
  • Experience with CPU or AI accelerator integration with SOC.
  • Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF)
Preferred qualifications:
  • PhD in Electrical Engineering or Computer Science.
  • Experience leading front-end design for modern processor components or AI accelerators.

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  • Experience with ARM Instruction Set Architecture.
  • Experience with SOC design, architect, and integration.

  • About the job

    Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

    Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.

    Responsibilities

    • Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
    • Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.
    • Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
    • Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
    • Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.

    Client-provided location(s): New Taipei City, Taiwan
    Job ID: Google-110073955896697542
    Employment Type: Other

    Perks and Benefits

    • Health and Wellness

      • Health Insurance
      • Dental Insurance
      • Vision Insurance
      • Life Insurance
      • Short-Term Disability
      • Long-Term Disability
      • FSA
      • HSA
      • Fitness Subsidies
      • On-Site Gym
      • Mental Health Benefits
    • Parental Benefits

      • Birth Parent or Maternity Leave
      • Non-Birth Parent or Paternity Leave
      • Fertility Benefits
      • Adoption Assistance Program
      • Family Support Resources
      • Adoption Leave
    • Work Flexibility

      • Hybrid Work Opportunities
    • Office Life and Perks

      • Commuter Benefits Program
      • Casual Dress
      • Pet-friendly Office
      • Snacks
      • Some Meals Provided
      • On-Site Cafeteria
    • Vacation and Time Off

      • Paid Vacation
      • Paid Holidays
      • Personal/Sick Days
      • Leave of Absence
      • Volunteer Time Off
    • Financial and Retirement

      • 401(K) With Company Matching
      • Company Equity
      • Performance Bonus
      • Financial Counseling
    • Professional Development

      • Tuition Reimbursement
      • Internship Program
    • Diversity and Inclusion

      • Employee Resource Groups (ERG)

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